Prefetchers are used to fetch program instructions and program data so that a processor can readily avail itself of the retrieved information as it is needed. The prefetcher predicts which instructions and data the processor might use in the future so that the processor need not wait for the instructions or data to be accessed from system memory, which typically operates at a slower rate than the processor. With a prefetcher implemented between a processor and system memory, the processor is less likely to remain idle as it waits for requested data from memory. As such, prefetchers generally improve processor performance.
Generally, the more predictions generated by a prefetcher, the more likely that the prefetcher can arrange to have the necessary instructions and data available for a processor, thereby decreasing the latency of a processor. But with some conventional prefetchers, predictions typically are generated without regard to the costs of implementing such prediction processes, thereby failing to realize the benefits from streamlining the prediction process and the amount of resources necessary for supporting it. As an example, some traditional prefetchers store predictions in a manner that does not conserve resources, whether computational or otherwise. In particular, these types of prefetchers primarily rely on standard techniques to produce predictions that are sequential in nature.
In view of the foregoing, it would be desirable to provide a system, an apparatus and a method for minimizing the drawbacks of implementing standard techniques of generating predictive accesses to memory.